Cedric Blot

Cedric Blot has extensive work experience as an R&D Engineer. Cedric started their career at Sacet in 2005 as a Stagiaire, where they worked on the definition and characterization of a COFDM-MIMO frame model. After completing their internship, they continued to work at Sacet as an R&D Engineer until February 2008.

Cedric then joined TeamCast as an R&D Engineer from February 2008 to October 2011. Following that, they worked at Canon as an R&D Engineer from January 2012 to December 2012. Cedric then moved to Elsys Design as an R&D Engineer in February 2012.

In November 2014, Cedric joined SYRLINKS as an R&D Engineer and worked there until April 2016. Cedric then joined ENENSYS Technologies as an R&D Engineer in April 2016 and continued working there until October 2019.

Most recently, Cedric worked at Nokia as an R&D Engineer from February 2020 to January 2021.

Cedric Blot pursued their education in a sequential manner. Cedric initially attended Lycée Jeanne d'Arc, Vitré (35) from 2000 to 2002, where they obtained a BTS Electronique degree. Following this, they enrolled at IUP Lorient from 2002 to 2004, where they earned a License et Maitrise GEII (Génie Electrique et Informatique Industrielle). Finally, in 2004 and 2005, they studied at Insa Rennes and completed a Master MARS degree in Electronics.