Hsuan Yi Chou

Hsuan Yi Chou has worked in the semiconductor industry since 2006. In 2006, they were a Section Manager & Sr. Testing Engineer at Winbond, where they created new KGD test programs for DDR products on T5581H, built up DDR/DDR2 new characteristic programs on FT T5581/T5585, and was the first to build a high parallel 64 DUTs test program at T5371 with IO compress mode. In 2012, they moved to Cypress Semiconductor as a Staff Testing Engineer, where they built up QDR4 high speed test patterns with TWIN IO/DR and led and created new ASYNC SRAM wafer sort/ BE programs. Finally, in 2014, they joined Everspin Technologies as Taiwan Team Manager and Staff Test Engineer, where they were mainly responsible for DDR4 (spin torque) test program and characteristic program build up and device verification on Verigy 93k HSM, as well as building up wafer sort programs for SPI/Asynchronous SRAM (toggle MRAM) products with Advantest T53xx series.

Hsuan Yi Chou attended Tatung University from 1999 to 2004, where they earned a Bachelor of Electric engineering.