Mandar Joshi

Mandar Joshi began their professional career in 2011 as a Lecturer in the Department of Electronics Engineering at VES Institute of Technology. In 2012, they became an Instructional Student Assistant (TA and Grader) at San Jose State University. That same year, they joined Broadcom as an Engineer, Staff I - IC Design, where they were responsible for development and functional verification of IO pads control logic and assisted in developing a custom bus arbitration scheme. In 2014, they moved to Intel Corporation as a Staff Engineer - Physical Design, where they were responsible for subsystem level timing closure, generating family level and block level timing ECOs, and piloting ML capability within Synopsys Fusion Compiler. In 2022, they joined Flex Logix Technologies, Inc. as a Senior Physical Design Engineer.

Mandar Joshi received their Master of Science in Electrical Engineering from San Jose State University between 2011 and 2013. Prior to that, they obtained their B.E. in Electronics Engineering from VES Institute of Technology between 2006 and 2010.