Pei Zhang

Pei Zhang is a seasoned engineer with extensive experience in ASIC design and software development. Currently serving as a Principal ASIC Design Engineer at Fortinet since March 2012, Pei Zhang specializes in designing and verifying network traffic processing ASICs. Prior to this role, Pei Zhang worked at Y Explorations Inc from October 2004 to March 2012, contributing as a Senior Software Engineer and China Business Development Lead, playing a key role in the development of the C to RTL Synthesis Tool, eXCite, while also leading business initiatives in China. Pei Zhang holds both a B.S. and M.S. in Electrical Engineering from Tsinghua University and is currently enrolled in the Ph.D. program in Information and Computer Science at UC Irvine.