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Rajesh Reddy

Asic Verification Engineer at Fungible

Rajesh Reddy has a diverse range of work experience in the field of engineering. Rajesh is currently employed at Fungible, Inc. as an Asic verification engineer since May 2021. Before that, they worked at Juniper Networks, where they held the position of ASIC ENGINEER, STAFF from March 2013 to May 2021. Prior to Juniper Networks, they were a Staff engineer - verification at Orca Systems from May 2009 to March 2013. Before that, they worked at Transwitch India (Centillium India Pvt Ltd) as a Staff Engineer - Verification from June 2003 to May 2009. Rajesh also has experience at Centillium India Pvt. Ltd. as a Staff engineer, where they specialized in VERA, SV, VCS NTB, Ethernet Passive Optical Network ONU 802. 3ah & VOIP based SoCs, VDSL2 phy, Ethernet Bridge Module Verification (802. 3, 802. from an unspecified start date to 2009. Rajesh began their career at Wipro Technologies as a Senior VLSI/System Design Engineer, focusing on verification engineering in the IP team, specifically USB 1. 1, USB 2. 0, USB OTG, USB with Interfaces PCI, AHB, from April 2001 to June 2003.

Rajesh Reddy obtained their M.Tech degree in Computer Science & Engineering from the National Institute of Technology Warangal, where they studied from 1999 to 2001. In addition to their formal education, Rajesh has also obtained several certifications, including "Artificial Intelligence Foundations: Neural Networks," "Artificial Intelligence for Project Managers," "Python for Data Science Essential Training Part 1," "Python for Data Visualization," "Data Ingestion with Python," and "Python Quick Start." These certifications were acquired from LinkedIn, with the most recent ones obtained in May and June of 2021.

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Timeline

  • Asic Verification Engineer

    May, 2021 - present