Ashutosh Kumar Agrawal

Ashutosh Kumar Agrawal is a skilled VLSI Design Verification engineer currently working with INNOPHASE since July 2022, contributing to the 5G team, specifically in the H3 projects. Prior to this role, Ashutosh completed an internship at Maven Silicon in August 2021, where the focus was on AHB2APB Bridge RTL Design using Verilog HDL. Ashutosh holds a Master of Technology in Photonics Science and Engineering from the Indian Institute of Technology, Kanpur, obtained in July 2023, and a Bachelor of Technology in Electronics and Communications Engineering from the Institute of Engineering and Management, completed in 2020.