Rajesh Reddy Challa

Rajesh Reddy Challa is a seasoned engineering professional with extensive experience in silicon design and power management across leading technology companies. Currently serving as a Silicon Design Engineering Manager at Intel Corporation, Rajesh is responsible for SOC integration QA and foundational IP support. Previous roles include SOC Power Management Architect at AMD, Manager/Staff Memory Design Engineer at ARM, and Senior R&D Engineer at Synopsys, among others. With a strong background in memory compiler design, performance improvement, and power modeling, Rajesh also has academic experience as a teaching assistant and research assistant at the University of Louisiana at Lafayette. Rajesh holds a Master’s degree in Computer Engineering - VLSI from the University of Louisiana at Lafayette and a Bachelor’s degree in Electronics & Computer Engineering from Jawaharlal Nehru Technological University.