Henry Zhang

Henry Zhang is a Senior Principal Design Engineer at Rambus since January 2023 and has served as an Adjunct Professor at International Technological University since 2009, teaching ASIC Design Practice. Previously, Henry was a Senior Technologist at Western Digital from June 2016 to December 2022, leading logic design for Storage Class Memory, and joined Western Digital through the acquisition of SanDisk, where Henry worked as a Logic Designer from March 2015 to June 2016. Experience also includes positions as a Logic Designer at Tabula, a Senior Staff Engineer in logic design and verification at SanDisk, a Senior Verification Engineer at Matrix Semiconductors, and roles at Zettacom, Allegro Networks, and Adaptec. Henry holds a PhD in Physics from The University of Texas at Austin and has a solid background in logic design, verification, and ASIC development.