JCET Group
Cheng Yang is a Corporate Fellow and Scientist at JCET / STATS ChipPAC since July 2021, focusing on advanced packaging technology and promoting silicon-package-system co-design to enhance product efficiency and performance. Previously, Cheng held the position of Director of Design, Process and Technology Engineering at Flex, where leadership involved advanced manufacturing engineering and the establishment of new technology development labs in Asia. At Intel, Cheng served as an R&D Manager from 2004 to 2017, leading engineering initiatives. Earlier experience includes a Senior Engineer role at GE, leading design projects for locomotive control systems, and a Senior Engineer position at Delta Electronics. Cheng's academic credentials include an EMBA from Washington University in St. Louis, a Ph.D. in Electronics Packaging from the National University of Singapore, and a Master's in Engineering Thermal Physics from Shanghai Jiao Tong University.
This person is not in any offices
JCET Group
JCET Group is the world’s leading integrated-circuit manufacturing and technology services provider, offering a full range of turnkey services that include semiconductor package integration design and characterization, R&D, wafer probe, wafer bumping, package assembly, final test and drop shipment to vendors around the world. Our comprehensive portfolio covers a wide spectrum of semiconductor applications such as mobile, communication, compute, consumer, automotive, and industrial, through advanced wafer-level packaging, 2.5D/3D, System-in-Package, and reliable flip chip and wire bonding technologies. JCET Group has two R&D centers in China and Korea, six manufacturing locations in China, Korea, and Singapore, and sales centers around the world, providing close technology collaboration and efficient supply-chain manufacturing to our global customers.