Bhavin Patel

Bhavin Patel is a seasoned engineering professional with over 15 years of experience in semiconductor and ASIC verification. Currently serving as a Sr Staff Engineer at Marvell Semiconductor since August 2020, Bhavin previously held the position of Principal Verification Engineer at Quantenna Communications from December 2011 to August 2020, where responsibilities included developing a comprehensive SoC verification environment in System Verilog and overseeing emulation and bring-up activities. Prior experience includes serving as Sr Technical Lead for ASIC verification at eInfochips, where extensive RTL verification using various methodologies such as VMM, OVM, UVM, and AVM was executed, coupled with leading a team to meet tight project deadlines. Contract roles at Rockwell Automation, Intel Corporation, and IDT further contributed to a robust skill set. Bhavin Patel holds an MBA in Finance from C P I M R and a B.E. in Electronics and Communication from L. D. College of Engineering.