Aruna Konakanchi is a skilled layout design manager with extensive experience in the semiconductor industry. Current roles include Manager Layout Design and Layout Lead at Microchip Technology Inc. Prior positions include Layout Manager and Senior Layout Design Engineer at Microsemi Corporation, as well as IC Layout Design Engineer at Silicon Laboratories. Aruna began a professional career as a CAD/IC Layout Design Engineer at National Semiconductor. Educational credentials include a Master of Science in Engineering from San Jose State University, earned between 2002 and 2004.
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