Muhammad Umer

Muhammad Umer is currently the Lead FPGA Design Engineer at NASTP since November 2022. Previously, Muhammad worked as a Labview/Matlab Development Engineer at RIMS from November 2017 to June 2022. Muhammad Umer also has experience as a Logistics Executive at acm seecs chapter and has completed various internships in the field of electrical engineering. Muhammad holds a Bachelor's degree in Electrical and Electronics Engineering from NUST.