Sarath Chandra

Sarath Chandra is a seasoned Sr ASIC Design Engineer 1 at Open-Silicon, Inc. since September 2018, with expertise in 40nm, 16nm, and 12nm technology nodes, overseeing the process from synthesis to GDS II and specializing in custom clock tree building. Prior experience includes a role as a Senior Design Engineer at Intel Corporation focusing on a 10nm flow from synthesis to signoff and proficiency in UPF flow, along with involvement in a project at Sankalp & KPIT Semiconductor as a Design Engineer managing synthesis to GDS II across seven blocks for an Intel project. Sarath started as a Project Engineer at Wipro Technologies, responsible for PnR activities from floorplan to routing. Educational background includes two Bachelor of Technology (BTech) degrees in Electrical, Electronics, and Communications Engineering from K L University.