Senior FPGA Design Engineer

At Ouster, we build sensors and tools for engineers, roboticists, and researchers, so they can make the world safer and more efficient. We've transformed LIDAR from an analog device with thousands of components to an elegant digital device powered by one chip-scale laser array and one CMOS sensor. The result is a full range of high-resolution LIDAR sensors that deliver superior imaging at a dramatically lower price. Our advanced sensor hardware and vision algorithms are used in autonomous cars, drones and many other applications. If you’re motivated by solving big problems, we’re hiring key roles across the company and need your help!

Ouster Inc. is seeking a senior digital hardware FPGA design engineer to build the next-generation of lidar systems. You will work hands-on with hardware and develop new techniques to improve lidar performance. Your effort includes micro-architecture design, implementation, and testing of the customer facing features in FPGA RTL. The ideal candidate will have experience in all aspects of FPGA design, verification, bring up, and debug, as well as ability in scripting and writing basic low-level drivers to accompany said designs.

Responsibilities:

• Define, develop, integrate, and test features across our FPGA stack
• General FPGA development including RTL, simulation, high-speed digital design, DSP algorithm development, verification, synthesis, and timing analysis.
• Perform hands-on work using laboratory tools for board bring up and troubleshooting.
• Work on high impact customer-facing features and integrate customer feedback in the development process
• Work cross-functionally with embedded software engineers, other ASIC/FPGA designers, and business leaders on functionality, interfaces, and documentation
• Build automation scripts for repetitive tasks to facilitate efficiency and reliability

Qualifications:

• Bachelors in Electrical, Computer Engineering or equivalent. Masters is highly desired.
• 5+ years of experience in FPGA development including HDL code development, simulation, test bench development, synthesis, and timing closure.
• Highly proficient in HDLs like Verilog and SystemVerilog (or VHDL).
• Proficient in C or C++ programming language.
• Experience with Xilinx or Intel FPGA toolchain.
• Strong embedded system development experience in CPU and FPGA based devices such as Xilinx Zynq or Intel Arria devices.

Desirable Qualifications:

• Familiar with HLS, Vivado and Vitis Tools.
• Familiarity with DSP and algorithms development
• Experience with leading verification methodologies like UVM.
• Experience using best practices with version control technologies such as git
• Experienced Linux user.
• Proficient in some scripting languages such as TCL, Python, bash.
• Experience with industrial safety systems.
• Experience with Functional Safety development processes.