Arthas Jie Xiao

Arthas Jie Xiao is a seasoned Staff ASIC Engineer with extensive experience in low power RTL design methodology and audio subsystem porting. Currently at Pixelworks since May 2015, responsibilities include developing RTL coding guidelines and refining memory generation and selection processes. Previously at Sigma Designs, Arthas contributed to the porting of audio subsystems from 40nm to 28nm technology. Prior experiences include successful tape-outs of multiple video chips at Pixelworks and FPGA design and verification roles at Tellabs and Huawei. Arthas holds a Master's degree in Electrical and Electronics Engineering from Fudan University and a Bachelor's degree in Telecommunications Engineering from Huazhong University of Science and Technology.