Avrum Warshawsky

Avrum Warshawsky is a seasoned engineering professional with extensive experience in ASIC and FPGA system design. Currently serving as Senior Technical Director of Systems Architecture at Rambus since May 2022, Avrum previously held the position of Chief Technology Officer at Hardent from January 2006 to May 2022, where responsibilities included maintaining technical excellence and advancing electronic product development technologies. Prior roles include Lead ASIC Architect at M3 Technologies, ASIC/FPGA Designer at Accelight Networks, and various ASIC Design Engineer positions at Agilent Technologies, HP, and Hewlett Packard (Canada) Ltd. Avrum holds both a Master’s and Bachelor’s degree in Electrical Engineering from McGill University, completed in 1991 and 1988, respectively.