Cezar Rodolfo Wedig Reinbrecht

Manager Logic Design at Rambus

Cezar Rodolfo Wedig Reinbrecht has a strong background in hardware security, with experience in logic design, VLSI consulting, and postdoctoral research in systems and security. With a PhD in Interconnections-on-chip and research interests in hardware security and side-channel attacks, Cezar has also worked as a lecturer and adjunct professor in computer architecture and programming disciplines. Their expertise includes hierarchical and reconfigurable networks-on-chip for MPSoCs and projects like DDR2 Memory Controller in VHDL on a FPGA.

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Timeline

  • Manager Logic Design

    April 1, 2024 - present

  • Principal Engineer Logic Design

    April, 2023

  • Lead MTS Logic Design

    June, 2021