Ehtsham Ul Hassan

Ehtsham Ul Hassan began their work experience as an Internship Trainee at Fauji Fertilizer Company Limited in 2017. Ehtsham then worked as an Internship Trainee at Power Station Mangla in 2018. In 2020, they joined Lampró Méllon as a Trainee Design Engineer and later transitioned to the role of Associate Design Engineer. Since 2021, Ehtsham has been employed at Rapid Silicon, where they started as an Associate Design Verification Engineer (Team Lead) and is currently working as a Design Verification Engineer (Team Lead).

Ehtsham Ul Hassan completed their Bachelor of Science degree in Electrical Engineering from the University of Engineering and Technology, Taxila, from 2015 to 2019.

In addition to their formal education, they also obtained several certifications from Cadence Design Systems. In March 2021, they completed exams in Analog Modeling with Verilog-A v17.1, Basic Static Timing Analysis v1.2, Behavioral Modeling with Verilog-AMS v14.2, C++ Language Fundamentals for Design and Verification v12.2, SystemVerilog Accelerated Verification with UVM v1.2.5, SystemVerilog Assertions v4.2, SystemVerilog for Design and Verification v20.6, and Xcelium Simulator v19.03. Ehtsham also obtained the SVA, Formal and Jaspergold Fundamentals for Designers v19.03 Exam certification in July 2021.