Zeshan Ali

Zeshan Ali has work experience as a Design Verification Engineer at RapidSilicon since January 2022. Prior to that, they worked at Lampró Méllon, starting in January 2020. At Lampró Méllon, they held various roles including Associate Design Engineer from October 2020 to December 2021, SoC-DV Team Lead from January 2021 to April 2021, and Trainee from January 2020 to October 2020.

Zeshan Ali completed their Bachelor of Science degree in Electrical, Electronics, and Communications Engineering from the University of Engineering and Technology, Lahore. Zeshan attended the university from 2015 to 2019. In addition to their formal education, Zeshan obtained a certification in the Verilog Language and Application v26.0 Exam from Cadence Design Systems in March 2021.