Nhat Nguyen

Nhat Nguyen's work experience began in 2000 as a Hardware Engineer at Cisco Systems, where they designed Register Transfer Level for board communication ASIC inside a router and performed backend tasks for a Queuing ASIC. From 2004 to 2005, Nhat worked as an ASIC Design Engineer at PMC-Sierra.

In 2006, Nhat joined Esterline-CMC Electronics as an FPGA Verification Engineer, verifying FPGA functions related to avionics communication protocols, RISC processors, image processing, data encoding, and board control functions. They also utilized methodologies such as UVM / SystemVerilog, Constrained Randomization, and Code Coverage.

In 2012, Nhat returned to Accedian Networks as a Senior FPGA Engineer, where they once again verified FPGA functions related to Ethernet traffic forwarding, Bandwidth shaping and policing, and Quality of Service.

In 2013, Nhat joined Esterline CMC Electronics as a FPGA Verification Engineer, continuing to verify FPGA functions in various areas such as communication protocols, processors, and encoding.

Since 2016, Nhat has been working as a Senior FPGA Engineer at Accedian Networks, focusing on the verification of FPGA functions including Ethernet traffic forwarding, Bandwidth shaping and policing, and Quality of Service. They apply methodologies such as UVM/SystemVerilog, Constrained Randomization, and Code Coverage.

Most recently, in 2019, Nhat joined a Proprietary Trading Firm as a Senior FPGA Verification Engineer, and in 2021, they started working as an FPGA Engineer at Rockport Networks. No specific end dates are provided for the latest roles.

Nhat Nguyen attended McGill University from 1996 to 2000, where they earned a Bachelor of Engineering degree in Computer Engineering.