Fabiano Bizinelli

Fabiano Bizinelli has a diverse work experience spanning multiple positions and companies. Fabiano started their career as a Researcher at UTFPR, where they focused on the research and development of xDSL technologies. Fabiano also taught Digital Circuits and Electronics Laboratory to undergraduate students.

Fabiano then joined Nokia Siemens Networks as an Associate R&D Engineer, where they were responsible for the full-cycle development of low-level embedded software for Mobile and Wireline Media Gateways. Fabiano also troubleshooted hardware/software problems and handled handovers of two projects.

Fabiano later joined Datacom as a Senior FPGA Design Engineer. Here, they were involved in the full-cycle logic design of high-speed FPGAs and CPLDs for NG-SDH and Ethernet products. Fabiano also proposed and designed a Packet Delay Variation measurement mechanism to improve the performance of products.

After Datacom, Fabiano worked at Alta Rail Technology as a Technical Leader / System Specialist. In this role, they led the integration of ART products into train control systems by proposing a communication services architecture based on open protocols. Fabiano also managed the development of the ART Communication Module, which provided communication and location systems into a single device.

Fabiano later joined Coveloz as a Senior RTL Designer, where they continued their work in designing RTLs. Most recently, they joined Ross Video as a Senior RTL Designer and was promoted to Manager, IP HW Solutions, where they currently work.

Fabiano Bizinelli's education history includes a Master of Business Administration (M.B.A.) in Project Management, obtained from ISAE/FGV from 2013 to 2015. Prior to that, they pursued their Master's degree in Electrical Engineering with a focus on Telecommunication Computer Science at the Federal University of Technology - Parana from 2000 to 2003. Fabiano'sBachelor's degree in Electrical Engineering was earned at the Universidade Federal do Paraná from 1994 to 1998.