sathakathulla Appa

Sathakathulla Appa has over a decade of experience in the semiconductor industry, currently serving as an Analog Layout Design Engineer at Sankalp Semiconductor since March 2018. Prior to this role, Sathakathulla worked as an Associate Design Engineer at Cadence Design Systems from September 2013 to February 2018, specializing in analog layout engineering for 16nm processes. Earlier experience includes a position as a Physical Design Engineer at Cosmic Circuits from May 2012 to September 2013. Educational qualifications include an Engineer's Degree in Electrical and Electronics Engineering from St. Xavier's Matriculation Higher Secondary School (2005-2009) and a diploma from Sri Ramana Polytechnic College in Moolaikaraipatti, Nanguneri Taluk, Tamil Nadu, where the degree was obtained from 2009 to 2012.