Winfried Keller

Winfried Keller is an experienced chip design engineer with over 20 years of experience in the field. Winfried began their career in 1997 as a Design Engineer for SICAN, where they implemented modules in VHDL and provided on-site verification and synthesis support at Alcatel/Stuttgart and Philips/Southampton. In 1998, they took on a Design Engineer role at Philips Semiconductors. In 2000, they moved to sci-worx as a Design Engineer, where they designed the memory interface of three camera interface IPs and acquired responsibility as module owner. In 2006, they took a Design Engineer role at Analog Devices. In 2007, they moved to Silicon Image as a Senior Design Engineer, where they extended a complex MPEG-2 transport stream demultiplexer IP to accommodate customer specific transport stream. In 2008, they took a gap year. In 2009, they took on a role as a Guest student at Leibniz Universität Hannover. In 2010, they moved to Fujitsu Semiconductor Europe as a CMOS Digital Design Engineer, where they designed the digital part of a 12 GSa/s DAC as interface to the analog world including a switchable HP/LP FIR filter and a register interface to the APB bus. Winfried also developed a tool written in C that generates an APB register interface in Verilog plus testbench and html documentation from a self-defined JSON spec file. In 2015, they moved to Socionext Europe as a CMOS Digital Design Engineer, where they enabled the company's high speed analog D/A converter IPs (128 GSa/s) to connect to the digital chip/SoC and APB bus by implementing various interface and control blocks according to spec. Winfried completed six full design cycles, of which two were cancelled just before tapeout and two became a product. In 2020, they moved to SatixFy as a Chip Design Engineer.

Winfried Keller obtained a Master degree in Electrical Engineering with emphasis in micro electronics from Technische Universität Darmstadt between 1990 and 1996.