Milos Milosavljevic

Staff FPGA Engineer (lead Architect) at Spire

Milos Milosavljevic, PhD has a diverse and extensive work experience. Milos started their career at the University of Hertfordshire, where they served as a Visiting Lecturer from September 2006 to September 2009. During this time, they supervised undergraduate and post-graduate labs and contributed to the preparation of several labs.

Milos then continued their journey at the University of Hertfordshire as a Senior Lecturer and Researcher from September 2010 to February 2017. In this role, they taught modules on Digital Electronics and Computer Organization, as well as Optical Communication Systems and Networks. Milos actively engaged in the supervision of final year, master, and PhD students. Additionally, they worked as a Post Doctorate Researcher at the university from January 2010 to August 2013, focusing on areas such as WiMAX/LTE propagation over PON and Next Generation Access Networks.

Since 2017, Milos has been working at Spire, a satellite-powered data company. Milos initially joined as a Senior DSP/FPGA Engineer and contributed to the development of global data solutions. Currently, they hold the position of Staff FPGA Engineer (Lead Architect). Unfortunately, there is no specified end date for this role.

Overall, Milos Milosavljevic, PhD has amassed significant expertise in research, teaching, and engineering within the fields of digital electronics, communication systems, and satellite-powered data solutions.

Milos Milosavljevic, PhD, obtained their BEng in Digital Communications and Electronics from the University of Hertfordshire in 2005. Milos then pursued an MSc in Radio and Mobile Communication Systems at the University of Hertfordshire from 2005 to 2006. Milos continued their education at the University of Hertfordshire, completing a PhD in Integrated Wireless-PON Access Network Architectures from 2006 to 2010. In addition to their academic degrees, Milos has obtained several certifications, including "Expert VHDL" from Doulos in 2022, "Improving Deep Neural Networks: Hyperparameter Tuning, Regularization and Optimization" and "Neural Networks and Deep Learning" from Coursera in 2020, "Wireless Communication Professional" from IEEE in 2016, and "Fellow of the Higher Education Academy" from the Higher Education Academy in 2014.

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Timeline

  • Staff FPGA Engineer (lead Architect)

    August, 2022 - present

  • Senior Dsp/fpga Engineer

    March, 2017

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