Vatsal Patel is an ASIC Design Engineer at Synopsys Inc since January 2023, previously serving as an ASIC Design Intern. In the summer of 2022, Vatsal worked as a FOSSEE Summer Fellow, contributing to feature additions for circuit simulations involving multiple microcontroller instances and designing the GUI for the eSim tool. Vatsal holds a Bachelor's degree in Electronics and Communication Engineering from Vishwakarma Government Engineering College, completed in 2023.
This person is not in any teams
This person is not in any offices