Xiaobing Yue is a Senior ASIC Design Engineer at Synopsys, a position they have held since 2021. Previously, they worked as a Digital IC Design Engineer at Tongfang Weishi from 2019 to 2021, focusing on AI chip design and deep learning FPGA acceleration frameworks. Xiaobing also gained experience as a Digital IC Verification Engineer Intern at Huawei in 2018. They obtained a Master's degree in Nuclear Electronics from Tsinghua University in 2019, graduating with a GPA of 3.54 out of 4.
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