Amirhossein R.

Amirhossein R. is a highly skilled professional in Electrical and Electronics Engineering with a strong academic background and relevant industry experience. Currently serving as Scientific Staff at Technische Universität Dresden since 2020, Amirhossein R. has developed an I/O multiplexer utilizing UDP packet handling in Verilog for FPGA systems, enhancing data communication efficiency, and designed a deep learning training algorithm on ARM Cortex-M4F platforms, optimizing performance through parallel processing. Prior to this role, Amirhossein R. worked as a Product Design and Development Expert at Samim Group from 2018 to 2019 and as an FPGA and DSP Design Engineer at MEPC Co. from 2013 to 2018. Amirhossein R. is pursuing a Doctor of Engineering degree at Technische Universität Dresden, building upon a Master's degree from Iran University of Science and Technology and a Bachelor's degree from University of Guilan.