ASIC Design Manager

Job Title: ASIC Design Manager

Degree Required: BS or Higher

Job Description:   

• RTL Coding, including block design, top level design, Lower power design, CPF/UPF design
• Verify design and debug in RTL-level, gate-level and PG gate level
• Simulation, Design constraints, Coding Style checking, Cross clock domain checking, Synthesis and timing closure
• Bug analysis and fixing, formal check
• Area, Power, FIT estimation/measure, DFT related, ATE support
• Deliver design/verification/application documents/SPECs
• Work closely with algorithm engineers to develop/debug new IP/product
• Work closely with verification/system/Firmware engineers to verify/validate new IP/product
• Work closely with architecture and FW engineers to define function of blocks
• Work closely with architecture and FW to settle down SoC level, subsystem, block level FW/HW partition, architecture
• Be able to learn new knowledge
• Team culture and efficiency management, team output quality management, project planning, and schedule management
• Communication across teams

Job Requirements:  

• Experience in Verilog code design and verification
• Experience in Unix/Linux OS, and scripting language like perl
• Experience in ASIC frontend flow and related tools (synthesis, formal, STA and DFT tools)
• Experience in Lower power design and verification with UPF/CPF
• Good understand on circuit design and timing constraint for synthesis/STA
• Familiar with C, UVM
• Familiar with formal check, DFT related, ATE related
• Strong problem-solving abilities
• Strong communication skills, with the ability to convey complex technical concepts to other design peers in verbal and written form
• A high level of self-motivation, the ability to be a self-starter, with a good attitude and is highly responsible
• Good written and verbal communication skills and presentation skills
• Ability to work in a team environment
• Team management experience