ASIC DV Engineer/senior ASIC DV Engineer

Job Title: ASIC DV Engineer/Senior ASIC DV Engineer 

Degree Required: BS or higher 

Academic Discipline(s): EE, CE, CS 

Experience Required: 5 years or more relevant industrial experience 

职位： ASIC 设计验证工程师 

学历及专业要求： 硕士及以上，电子工程、计算机科学专业（EE, CE, CS） 

工作经验要求: 5年以上相关工作经验 

Job Description:  

A Senior ASIC Design Verification Engineer is responsible for the design verification of various parts of a complex state-of-the-art SoC, from test planning to testbench and test development, simulation and debugging, regression, documentation, coverage measurement, all the way to tapeout and post-silicon validation. The candidate should be a self-driven, easy to work with, and a team player. 

职位描述： 

负责复杂的最新SOC各个部分的设计验证，从测试计划到测试台和测试开发，模拟和调试，回归，文档，覆盖率测量，一直到tapeout和post silicon验证.候选人应该是一个自我驱动，易于合作，团队合作的人. 

Job Responsibilities: 

• Ability to communicate effectively in written and spoken English

• RTL design architecture for ASIC, specifications, and test planning

• RTL and testbench development using UVM methodology and System Verilog

• RTL and testbench simulation and debugging using a waveform debugger

• Use of commercial tools such as Synopsys and Cadence

• Device modeling and Verification IPs, and configuration, such as DDR, flash, PCIe, AXI

• Strong knowledge of programming languages such as C/C++/Perl/Python

• Bug tracking, regression and coverage measurement methodology

• Random testing

• Experience with emulator and FPGA is helpful

• Documentation and tracking for specs, plans, status and bugs

技术要求： 

• 可使用中英文沟通

• ASIC 规范和测试计划的RTL设计架构

• 熟悉UVM方法和System Verilog开发RTL和测试台

• 使用波形调试器进行RTL和试验台模拟和调试

• 熟练使用商业工具（如Synopsys和Cadence等）

• 设备建模和验证IP以及配置，如DDR、闪存、PCIe、AXI

• 熟悉C/C++/Perl／Python

• 缺陷跟踪、回归和覆盖测量方法

• 随机测试

• 有模拟器和现场可编程门阵列的经验加分

• 规范、计划、状态和缺陷的文件和跟踪