Engineering · Full-time · Pudong, China
Job Title: Senior ASIC Design & Integration Engineer
Degree Required: BS or higher
Tenafe is a newly established startup company which focus on leveraging revolutionary SSD Controller SOC development and related firmware/software systems solutions addressing fast growing NAND flash memory-based storage products, which is essential for cloud computing, big data center, smartphone, tablet pc and all ultra-portal computing appliance.
Official website: https://www.tenafe.com/
Job Description:
As a Senior ASIC Integration Engineer as a part of the SSD ASIC Design Team, you will take part in developing leading edge SSD controller products and you will experience different and exciting journey with Tenafe.
Lead SoC implement/integration
Bring-up/Improve the flow for synthesis, lint & CDC audit, Formal check, static timing check and DFT
UPF/CPF for power-intent, static power-intent audit, conformal ECO
Implement RTL vs SYN netlist formal check and netlist vs netlist formal check
Bring up the SDC for PT, support timing closure, power estimation, power domain division criteria etc.
Support DFT related problems (such as ATE patterns debug) and post-simulation
Work with architecture and design engineers to develop test plans
Work with physical design engineer to fix timing closure
Job Requirements:
Bachelor with 5+ year experience or Master with 3+ year experience
Solid knowledge of ASIC/SOC design flow, including coding, simulation, verification, synthesis, STA and formal check
Knowledge of DFT design, including JTAG, IEEE1500, MBIST and ATPG is a big plus
Knowledge of PR, including floorplan, placement, CTS, routing, IR drop analysis is a big plus
Demonstrate experience with SOC synthesis, formal check, STA and audit
Experience with Perl, TCL, Makefile coding
Experience with UPF/CPF
Fast learning and hard working
Self-motivated, and the ability to be a self-starter with a good attitude
Good written and verbal communication skills, presentation skills and the ability to work in a team environment
Some familiarity with mixed-signal IP (DDR, PCIe) is desirable