Andoleet Saleh

Andoleet Saleh is a skilled analog and RFIC design engineer currently serving as a Senior Engineer at TRYSL TECH since January 2023, where responsibilities include developing various analog/RF integrated circuits and overseeing layout work across different technology nodes. Prior experience includes a role as a Standard Analog Layout Design Engineer at Si-Vision from August 2021 to January 2023, focusing on SERDES block layout for advanced technology nodes, and an analog IC design trainee position at Si-Vision Academy, enhancing knowledge in analog design and circuit simulation. Additionally, Andoleet has worked as an Analog Design Engineer on pipeline ADC blocks at Zewail City of Science and Technology and completed an internship at ONE Lab Egypt, gaining experience in memristor devices. Educational qualifications include a Bachelor's degree in Nanotechnology and Nano-electronics Engineering and training in information technology, alongside a high school diploma with a mathematics focus.