Sri Harsha Panchanam

SRI HARSHA PANCHANAM is a highly experienced Senior Design Verification Engineer with a strong background in SOC verification, particularly in PCIE/SATA based SSD controllers. Currently serving at Cisco and XPENG, SRI HARSHA has previously held positions at Cisco, Marvell Semiconductor, and Intel Corporation, focusing on various verification environments including UVM and post-silicon debugging. With a Master's degree in VLSI-ASIC/FPGA Design and Verification from San José State University, SRI HARSHA has also completed professional training in System Verilog. The career spans over a decade, beginning as a Verification Engineer at Atria Logic Inc. and includes valuable internships, demonstrating a progressive and robust expertise in design verification.