Vivek Jayanand

Vivek Jayanand has a diverse work experience in the semiconductor industry. Vivek is currently working as a SERDES Validation Engineer at Achronix Semiconductor Corporation since September 2022. Before that, Vivek worked at Western Digital where they held multiple roles. Vivek served as a Senior Manager for SERDES Validation from December 2021 to September 2022, a Technologist from September 2019 to November 2021, and a Principal Engineer in the Host interface team from August 2014 to October 2019. Prior to Western Digital, they worked at Marvell Semiconductor as a Staff Field Applications Engineer from January 2012 to August 2014 and as a Senior Hardware Engineer from April 2007 to December 2011. Vivek also gained experience at Altera as an Advanced Applications Engineer from November 2005 to February 2007, and at Integrated Device Technology Inc as a Product Engineer from February 2001 to November 2005.

Vivek Jayanand obtained a Master of Science (M.S.) degree in Electrical Engineering from the University of Southern California in 1999-2000. Vivek also pursued a Master of Science (M.S.) degree in Electrical and Electronics Engineering from the same institution. However, the exact start and end dates for this program are not provided.