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Darshan Alagud

Staff Design Engineer - Interconnect at Arteris

Darshan Alagud has a diverse work experience in the field of semiconductor engineering. Darshan started their career in 2006 as a Project Engineer at Wipro Technologies, where they worked on ARM-based SoCs, focusing on RTL design, design verification, and modeling activities. After that, they joined Intel Corporation as a Grad Intern, where they worked on Graphics chip debugging and C++ models for OpenGL graphics pipe and HEVC media pipe.

In 2013, Darshan joined Freescale Semiconductor, which was later acquired by NXP Semiconductors. At NXP, they worked as a Logic Design Engineer, contributing to the company's SoC design team and working with QorIQ SoCs, both ARM-based and Power PC-based. Darshan then transitioned to a Design Engineer role in the Digital Networking group, focusing on SoC design.

In 2016, Darshan moved to Samsung Electronics, where they held the position of Sr. Design Engineer. Darshan worked in the GPU Shader-Core team, gaining experience in RTL design and working on format conversion units and clock-gating implementations.

Currently, Darshan is working at Arteris IP as a Staff Design Engineer, specializing in interconnect design. Darshan has held successive roles at Arteris IP, starting as a Sr. Design Engineer and progressing to their current position.

Darshan Alagud completed their education with a master's degree in Electrical Engineering from The University of Texas at Arlington, specializing in embedded systems, VLSI, and multimedia. Darshan pursued this degree from 2010 to 2012. Prior to that, they obtained a Bachelor of Engineering (B.E.) from PESIT, Bangalore, majoring in Electronics and Communication. Darshan attended PESIT from 2002 to 2006. Darshan Alagud completed their primary and secondary education from MES Kishora Kendra between 1994 and 2002, although the specific degree and field of study during this period are not mentioned.

Links


Timeline

  • Staff Design Engineer - Interconnect

    March, 2021 - present

  • Sr Design Engineer Interconnect

    October, 2017