Satheesh Nataraja Pillai

Satheesh Nataraja Pillai has over 20 years of experience in the semiconductor industry. Satheesh began their career in 2000 as a Design Engineer at Motorola Semiconductor, where they were responsible for RTL design and integration. In 2001, they moved to Intel Corporation as an Engineering Team Lead for physical design, DFT, and verification. In 2009, they took on the role of Design Manager at ST-Ericsson, where they were responsible for SOC Physical Design and DFT. In 2012, they joined Future Technology Devices International as an Engineering Lead for physical design, DFT, and verification. Here, they worked on the SOC Physical Design+ DFT implementation of FT800, the first product of the Embedded Video Engine business group. In 2013, they moved to Broadcom Inc. as a Lead Technical Consultant. In 2021, they joined Flex Logix Technologies, Inc. as the Director of Engineering for SOC and IP Subsystem Physical design. In this role, they are responsible for building an efficient AI edge inference accelerator and architecting a low cost/die area SOC in TSMC N6 process node.

Satheesh Nataraja Pillai completed their M.Tech in Solid State Technology from the Indian Institute of Technology, Madras in 2000. Satheesh also holds a Leading Innovative Change certification from UC Berkeley Executive Education.