Marc B.

Marc B. has a diverse work experience in the field of engineering. Marc started their career as a Hardware Intern at Recore Systems, where they designed and tested an interface between SpaceWire IP and Recore Systems' Network-On-Chip. After that, they worked as a Graduate FPGA Engineer at Sondrel Ltd, where they set up FPGA tool flow, performed bug fixing for front-end IPs, and verified front-end IP with SystemVerilog. Marc then joined TOPIC Embedded Systems as a Senior FPGA Engineer, where they worked on various FPGA-related tasks, such as safety design, firmware development, and scripting using VHDL/Verilog, HLS, Vivado, Petalinux, Linux, and Python/tcl/bash. Marc also did their Master thesis at Thales, where they designed fault-tolerant interconnects for communication in RADAR systems using Forward Error Correction on UltraScale Kintex FPGA. Before transitioning to the field of engineering, Marc served as an SSI Dive Control Specialist at ZPV Piranha, where they gave scuba diving introductions, assisted with scuba courses, and guided dive days. Marc also held various board positions at ZPV Piranha, including Commissioner Scubadiving and Treasurer. Currently, Marc is working as a Senior ASIC Design Engineer at GrAI Matter Labs.

Marc B. completed their VMBO, TL degree in Techniek at Carmel College Emmen from 2003 to 2007. Marc then went on to complete their VWO degree in Nature and Technology at Carmelcollege Emmen from 2007 to 2010. Marc continued their education at the University of Twente, where they completed their Bachelor's degree in Electrical Engineering from 2010 to 2015. Marc further pursued their education at the University of Twente, completing their Master's degree in Embedded Systems from 2015 to 2017.