William Yee

William Yee has extensive work experience in the field of FPGA design and verification engineering. William started their career in 1995 as an ASIC Design Verification Engineer at Cabletron Systems and then worked as an ASIC Engineer at ATI Technology from 1996 to 2000. In 2000, they joined RiverDelta Networks as a Senior FPGA Design and Verification Engineer. William continued to advance their career and became a Senior FPGA Design and Verification Engineer at Motorola in 2002, where they also took on the role of Project Lead and led a team of designers and verification engineers. In 2013, William joined Casa Systems, Inc. as a Technical Manager, Technical Lead, and Principal FPGA design verification engineer. During their time at Casa Systems, they successfully managed and led a team of FPGA design verification engineers, and also had the opportunity to architect simulation environments for the verification of multiple FPGA developments for cable DOCSIS and wireless 4G/5G industry. William'smost recent role is at Lightelligence, where they hold the position of Technical DV Manager and Lead Design Verification Engineer from September 2021 until now.

William Yee attended Boston Latin School, but the dates of their enrollment are unknown. William then went on to study at Boston University, where they obtained a Bachelor of Engineering (B.E.) degree in Electrical and Electronics Engineering. However, the specific years of their studies at Boston University are also not provided.