Design Verification Manager

We are seeking an experienced Design Verification Manager. This position requires extensive hands-on experience with CPU verification using industry-standard functional verification methodologies, formal verification, constrained random generators, and reference model-based checkers. The candidate must be able to take critical decisions and completely own the verification function. This position involves cross-functional interaction with CPU designers, architects, and working across sites to ensure high-quality CPU designs for customers. 

You will:

• Take full ownership and drive verification efforts to closure
• Work closely with designers and architects to understand requirements
• Create project plans with multiple resources and projects
• Manage a team consisting of highly experienced and less experienced engineers
• Understand use cases and drive appropriate verification plans
• Drive methodology improvements in design verification using the latest methodologies, tools, and automation
• Support for prototyping in FPGA and/or Emulation

Ideally, you’ll have:

• Masters degree preferred in Electronics/Electrical/Computer Engineering with 10+ years of industry experience with a focus on functional verification of CPUs
• Familiarity with CPU architectures and superscalar designs and industry-leading RISC processors
• Exposure to various design verification tools with good digital design concepts
• Knowledge and experience with Interconnect protocols like AXI/ACE/OCP/CHI
• Scripting experience in Python/Perl/TCL/Shell
• Experience in creating functional test plans and implementing them as part of pre-silicon verification
• Knowledge of Verilog/SystemVerilog/C/C++/Assembly
• Strong analytical and problem-solving skills
• Are self-motivated with excellent communication and presentation skills, and the ability to collaborate well with local and global teams

A plus if you have:

• Experience with RISC-V, ARM, and/or MIPS CPU
• Experience with multi-core and coherency
• Familiarity with functional safety flows and requirements