Shajeer K

Shajeer K is an experienced professional with over 9 years in VLSI Digital Design and Verification. Currently serving as a Senior Design Engineer at Test and Verification Solutions and as a Lead Engineer at Quest Global Japan since December 2017, Shajeer possesses expertise in aerospace verification engineering, test case preparation, and the creation of design specifications and micro-architecture designs. Prior roles include Senior Engineer at PerfectVIPs and VLSI Designer at Mutech Infotracks, along with a position as Design Manager at Aspire Technologies, where Shajeer was involved in developing communication protocols with VHDL and Verilog for FPGA. Shajeer holds an M.Sc in Electronics from MG University and a B.Sc in Electronics from National College, complemented by a specialization in Verification with System Verilog from MAVEN Silicon.