Renaud Di Bernardo

Renaud Di Bernardo has extensive work experience as an FPGA Engineer, starting with Redlen Technologies Inc. in 2022. Prior to that, they worked at Per Vices Corporation from 2020 to 2022 in the same role. From 2017 to 2020, Renaud was a FPGA Designer at Evertz, where they designed and supported an Audio Gate Hub for video systems using VHDL on a Xilinx Virtex Ultrascale FPGA. In 2017, they worked as an ASIC Design Engineer at Istuary Innovation Group, focusing on integrating Synopsys's PCIe IP into a high-security level ethernet switch and integrating Xilinx's PCI Express onto a Virtex Ultrascale+ for FPGA emulation. Before that, Renaud was a FPGA Designer at Elsys Design from 2015 to 2016, where they designed and implemented a configurable bridge between CPRI and 10 Gigabit Ethernet protocols. Renaud also worked at Groupe de Recherche en Microélectronique et Microsystèmes, Polytechnique Montréal, CNRS, and Laboratoire pour l'analyse de la surface des matériaux (LASM) in various technician and engineering roles.

Renaud Di Bernardo completed their Diploma of Collegial Studies in Instrumentation & Measurement at IUT de Marseille from 2009 to 2011. Renaud then pursued their Bachelor of Engineering (B.E.) in Instrumentation & Microsystems at Grenoble INP - Phelma from 2011 to 2014. After that, Renaud attended Polytechnique Montréal, where they obtained their Master's degree in Microelectronic - Digital electronic from 2013 to 2015.