Boleslaw Wojtowicz

Boleslaw Wojtowicz has been in the engineering field since 2006. Boleslaw began their career as a Junior Analog Design Engineer at Chipidea. In 2007, they moved to MIPS Technologies Analog Business Group - Chipidea, where they held the same role. From 2009 to 2014, they worked as an Analog IC Design Engineer and then Senior Analog IC Design Engineer at Synopsys. Boleslaw was a member of the HSIO Design Group and was responsible for designing biasing, termination, and calibration circuits, as well as the HS-TX driver and implementation of low power solutions. In 2014, they became a R&D Design Engineer at Silicon Line GmbH.

Boleslaw Wojtowicz received their technical degree from Zespol Szkol Technicznych in Electronic from 1996 to 2001. Boleslaw then went on to obtain their Master of Science (M.S.) in Microelectronics and Microwave Engineering from Gdańsk University of Technology from 2001 to 2006.