Angrej Singh

Principal Engineer at Synopsys

Angrej Singh is an experienced verification specialist currently working at Verilab since April 2022. Prior to this role, Angrej held positions at Marvell Semiconductor as a Staff Engineer in Design Verification and at Aquantia as a Member of the Technical Staff, which was acquired by Marvell. Additional experience includes a consultancy role at Intel Corporation focusing on pre-silicon validation and soft IP verification, as well as multiple engineering roles at Cadence Design Systems, where Angrej contributed to Ethernet verification IP development and various feature developments. Angrej's educational background includes a PGD in VLSI and Embedded System Design from the Center of Development in Advanced Computing and a Bachelor of Technology in Electrical, Electronics, and Communications Engineering from Punjab Technical University.

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