Vitor Antunes

Vitor Antunes is currently the R&D Manager at Synopsys Inc, where they have been since 2019. Prior to this role, they worked as an R&D Engineer at Synopsys from 2009 to 2019, focusing on digital design, architecture definition, and system verification. Vitor began their career as a Modeling Engineer at Chipidea from 2004 to 2007, developing Verilog models of analog systems, and later held the position of IT Systems Engineer at MIPS, where they managed Linux systems from 2007 to 2009. Vitor holds a Master's degree in Electronics and Computers Engineering and a Bachelor's degree from Instituto Superior Técnico.