Ryan Yu

Ryan Yu has worked in the tech industry since 2004. Ryan began their career at Link-A-Media Technologies as a Senior Staff Engineer, where they were responsible for Servo Channel and Read Channel designs, as well as serving as a chip lead for production SoC and test-chips. In 2014, they moved to SK hynix memory solutions inc., where they managed a team of 8 designers and was responsible for micro-architecture definition of flagship Flash Controller for SKHynix 2D/3D TLC NAND, toplevel integration, floor planning feedback, timing closure, and RTL design. In 2017, they joined Micron Technology as a Principal Design Engineer, where they were responsible for ASIC bring up/test/debug and SoC level performance modeling using Python. Currently, they are working as an Application Specific Integrated Circuit Design Engineer at TenaFe Inc., where they have completed silicon-proven LDPC Encoder and LDPC min-sum Decoder engines, from micro-architecture to RTL design, as well as a Decoder top-level with CMD/ STATUS Queue and Data In/Out state machine design.

Ryan Yu holds a Master of Science (MS) in Electrical, Electronics and Communications Engineering from the University of Southern California.