Arteris
Eric Howard has extensive work experience in the technology industry. Eric started their career at Intel Corporation as a Member of the Technical Staff from June 1990 to February 1992. Eric then joined High Level Design Systems as a Principal Software Architect from February 1992 to February 1997. Following that, they worked at Cadence Design Systems as a Senior Manager of Engineering from March 1997 to March 1999.
Eric then moved to InTime Software where they served as a Software Architect from April 1999 to January 2004. During this time, they played a key role in developing RTL timing methodology and design flow. Eric also drove correlation between RTL and gate level timing.
Afterward, Eric joined Silicon Navigator as a Senior Software Architect from January 2004 to January 2008. Here, they developed a C++ API for a standalone static timing engine and integrated the Concept schematic system onto Open Access (OA).
Next, they joined Chip Path Design Systems as an Architect from January 2008 to September 2014. In this role, they architected and developed a physical-design based static timing analysis tool. Eric also implemented features like RTL processing, timing, placement, and power calculations.
Most recently, Eric worked at Arteris as a Senior Software Engineer starting in September 2014. Their responsibilities included implementing a streamlined SDC constraint generator for a cache coherent network on chip design tool and creating a regression environment for code coverage and regression tests.
Throughout their career, Eric has demonstrated expertise in software architecture, design flow, static timing analysis, and RTL timing methodology.
Eric Howard obtained a Bachelor of Engineering (B.E.) degree in Electrical Engineering and Computer Science from the University of California, Berkeley in the years 1985 to 1990.
Arteris
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Arteris is helping power the next wave of autonomous driving, 5G and Artificial Intelligence (AI) systems fueling the growth the of the semiconductor industry. Our Network-on-Chip (NoC) interconnect semiconductor intellectual property (IP) is the on-chip communications backbone of most of the world’s most important and sophisticated systems-on-chip(SoC). Optimizing on-chip dataflow and connectivity is the cornerstone of our vision for system-on-chip development and assembly. Since our inception in 2003, we have pioneered the development and commercialization of NoC interconnect technology, cementing our position as the world’s first and largest commercial NoC interconnect IP company. Our unique technology meets the needs for cache coherent and non-coherent on-chip communications, on-chip data caching, and on-chip data protection to meet functional safety requirements.ARTERIS IP PRODUCTS AND SOLUTIONSOur on-chip NoC-based interconnect IP products make systems-on-chip easier to develop, perform better, and faster to get to market.The Arteris IP product portfolio meets the needs of design teams creating nearly any type of digital logic SoC with any type of communications semantics. Our seminal FlexNoC® Interconnect IP pioneered the market for NoC interconnects and is the industry leader. The highly configurable Ncore® Cache Coherent Interconnect IP allows optimal integration of cache-coherent Arm®-based processor IP with other cache-coherent and non-coherent IP.The growth of Artificial Intelligence (AI) and Machine Learning (ML) has inspired the creation of two innovative products. The Arteris IP AI Package is an option to Arteris FlexNoC that provides automated means to create complex topologies (meshes, rings, and tori) while adding multicast/broadcast communications, virtual channels, and source-synchronous communications to meet the unique needs of AI/ML chips. The CodaCache® Last Level Cache provides a highly configurable cache that can be instantiated anywhere within an SoC interconnect, providing data locality wherever needed.To meet the needs of the new generation of multibillion-transistor chips for automated systems with functional safety requirements, Arteris IP also offers Resilience Packages that provide hardware-based data protection technologies as well as automated diagnostic coverage analysis to help meet requirements ISO 26262 and IEC 61508 functional standards. Resilience Packages are available for FlexNoC, Ncore and CodaCache IP products.Timing closure has become a key design schedule constraint as chips have grown in size and complexity and semiconductor manufacturing process critical dimension have shrunk. To address this, Arteris IP created the PIANO® Timing Closure Package which provides physical and timing information about the interconnect to back-end synthesis place and route tools to help ensure faster timing closure.