Wissam Eyssa

Wissam Eyssa has extensive experience in analog design engineering, specializing in RFIC and mm-Wave applications. Wissam currently holds the position of Senior Staff Analog Design Engineer at ASR Microelectronics International since October 2020. Prior to that, they worked as a Senior RFIC Analog Design Engineer at Catena Group from July 2017 to August 2020, and at Marvell Semiconductor from January 2012 to May 2017. Wissam also has a strong academic background, having served as a Postdoc at the University of Pavia-Italy in Collaboration with ST-Microelectronics from January 2007 to January 2012, focusing on the design and modeling of passive components for transceivers and CMOS devices for Silicon Photonics applications.

Wissam Eyssa completed a Laurea degree in Electronic Engineering from Università di Pavia in 2003. Following this, they pursued a Ph.D. degree in Electronic, Electrical and Computer Science Engineering from the same institution between 2003 and 2006.