Hemasundar P

Hemasundar P has a diverse work experience in the field of physical design and layout engineering. Hemasundar is currently working as the Director of Physical Design at Astera Labs since 2022. Prior to this, they worked at Synopsys Inc from 2014 to 2022, where they held various roles including Manager II in SOC Physical Design and Staff Physical Design Engineer. In these roles, they were responsible for the physical design implementation of DDR and HBM PHY IP's in different technology nodes. Hemasundar also created methodologies for floor-plan and power grid creation. Before joining Synopsys, Hemasundar worked at AMD from 2010 to 2014 as an MTS Design Engineer, where they focused on physical design implementation of DDRPHY IP in various technology nodes and led the custom layout design team for L2 and L3 macros. Prior to that, they worked at incube solutions pvt ltd as a custom memory layout engineer from 2008 to 2010. Their earliest work experience was at QualCore Logic from 2005 to 2008, where they worked as a Custom Layout Engineer, specializing in analog, mixed signal, and RF blocks. Hemasundar also served as an onsite engineer for Texas Instruments during their time at QualCore Logic.

Hemasundar P pursued their education starting from 1989 to 1999 at St. Peters High School. However, no specific degree or field of study is mentioned for this period. Then, from 2001 to 2005, Hemasundar completed their Bachelor's in Technology (Btech) in Electronics and Communication Engineering (ECE) from Jawaharlal Nehru Technological University. Finally, from 2008 to 2010, Hemasundar obtained a Master's degree (MS) in Microelectronics from Manipal Academy of Higher Education.