Tiago Campos

Tiago Campos currently serves as a Senior Engineer in Silicon Logical Design at Axelera AI, a position held since October 2022. Prior experience includes multiple roles at Synopsys Inc from February 2019 to October 2022, where Tiago worked as an ASIC Digital Design Engineer II focusing on PCIe 6 and ARM Confidential Computing, as well as an ASIC Digital Design Engineer I specializing in PCIe 5, AXI Bridge, and DMA. Tiago's career began with a Graduate Student Internship culminating in a Master's thesis on "Store-and-forward CDC packet transmission in digital systems," achieving a final grade of 18 out of 20. Additional experience includes teaching assistant roles in programming courses at the Faculty of Engineering of the University of Porto and a summer internship in technical engineering at Synopsys Inc involving formal verification. Tiago holds an Integrated Master's Degree in Electrical and Computer Engineering from the Faculty of Engineering of the University of Porto, completed in 2019.