Tianlun Liu

Tianlun Liu has held various positions in the technology industry since 2009. Tianlun began their career as a Research Assistant at Johannes Kepler University. In 2012, they joined Intel Corporation as a SoC Design Engineer, where they implemented the Filter Coefficient Storage bit-exact model in C and designed the Clock Generation Unit in the SoC. Tianlun was later promoted to Senior SoC Design Engineer. In 2021, they moved to Qualcomm as an ASIC Design Engineer, Staff, where they were responsible for Front end RTL design and familiar with the Random Number Generator Standards. Currently, they are an ASIC Design Engineer at Cornelis Networks, where they are implementing the Efuse Array controller described in Systemverilog and PVT sensors integration.

Tianlun Liu obtained a Bachelor of Engineering (B.Eng.) in Computer Science and Technology from Changsha University of Science and Technology between 2001 and 2005. Tianlun then went on to complete a Master of Science (M.Sc.) in Information and Communication Engineering from Technische Universität Darmstadt between 2006 and 2009.