Mohamed Hosni

ASIC Design Engineer at Efabless

Mohamed Hosni has worked for a variety of companies since 2019. In 2019, they were an FPGA Design Intern at ONE Lab Egypt, where they developed Dynamic Partial Reconfigurable (DPR) designs of hashing algorithms on the ZYNQ x702 board and wrote a conference paper on DPR advancements in blockchain applications as the first author and got accepted in ICM 2020. In 2020, they worked as an ASIC Student RA and Digital Design Intern at Zewail City of Science and Technology. In 2021, they were an Embedded SW Intern at Valeo and a Bachelor's Graduation Project Intern at Si-Vision. Currently, they are an IC Design Engineer at Efabless Corporation and a Graduate RA/TA at The American University in Cairo.

Mohamed Hosni obtained a Thanwya Amma from Freedom Language School in 2016-2017. Mohamed then attended Zewail City of Science and Technology from 2017-2022, where they earned a Bachelor's degree in Nanotechnology and Nano-electronics Engineering. Additionally, they have obtained several certifications, including ADCs Training from Siemens EDA (Siemens Digital Industries Software) in March 2022, FPGA Training from Siemens EDA (Siemens Digital Industries Software) in September 2021, a Digital Verification Course from NajahNow in July 2021, an ASIC Course from NajahNow in January 2021, a Hardware Description Languages for FPGA Design from Coursera in October 2020, and an FPGA computing systems from Coursera in October 2019.

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Timeline

  • ASIC Design Engineer

    October, 2022 - present